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By Author: Andrew E
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The Pentium is Intel's fifth-generation x86 architecture microprocessor and successor to the company's 486 line of chips. The word pentium doesn't mean anything, but it contains the syllable pent, the Greek root for five. Originally Intel was going to call the Pentium the 80586, in keeping with the chip's 80x86 predecessors. But the company didn't like the idea that AMD, Cyrix, and any other clone makers could use the name 80x86 as well, so Intel decided on a trademarkable name - hence Pentium.

Pentium architecture chips offered just under twice the performance of a 486 processor per clock cycle. their introduction in 1993 revolutionising the PC market by putting more power into the case of the average PC than NASA had in its air-conditioned computer rooms of the early 1960s.

The first Pentium CPU debuted as a 60 and 66 MHz chip, integrated 3.1 million transistors and was built in an 0.80-micron production process. By the time of the dual-core Presler-based Pentium D of early 2006, the number of transistors had reached a staggering 376 million and the process technology had shrunk to 0.65nm. However, by that time ...
... it also appeared that Intel were set to slowly drop the Pentium brand name as the company transitioned to its new Intel Core microarchitecture.
Pentium

The Pentium's CISC-based architecture represented a leap forward from that of the 486. The 120MHz and above versions have over 3.3 million transistors, fabricated on a 0.35-micron process. Internally, the processor uses a 32-bit bus but externally the data bus is 64 bits wide. The external bus required a different motherboard and to support this Intel also released a special chipset for linking the Pentium to a 64-bit external cache and to the PCI bus.

The majority of Pentiums (75MHz and above) operate on 3.3v with 5v I/O protection. The Pentium has a dual pipelined superscalar design, allowing it to execute more instructions per clock cycle. There are still five stages (Prefetch, Instruction Decode, Address Generate, Execute and Write Back) in the execution of integer instructions, like that of the 486, but the Pentium has two parallel integer pipelines, enabling it to read, interpret, execute and despatch two operations simultaneously. These only handle integer calculations - a separate Floating Point Unit handles "real" numbers.

Pentium CPU

The Pentium also uses two 8KB, two-way set, associative buffers (also known as primary or Level 1 cache), one for instructions and another for data. This is twice the amount of its predecessor, the 486. These caches contribute to increased performance because they act as a temporary storage place for data instructions obtained from the slower main memory.

A Branch Target Buffer (BTB) provides dynamic branch prediction. The BTB enhances instruction execution by "remembering" which way an instruction branched and applying the same branch the next time the instruction is used. When the BTB makes a correct prediction, performance is improved. An 80-point Floating Point Unit provides the arithmetic engine to handle "real" numbers. A System Management Mode (SMM) for controlling the power use of the processor and peripherals rounds out the design.
Pentium Pro

Intel's Pentium Pro, which was launched at the end of 1995 with a CPU core consisting of 5.5 million transistors and 15.5 million transistors in the Level 2 cache, was initially aimed at the server and high-end workstation markets. It is a superscalar processor incorporating high-order processor features and is optimised for 32-bit operation. The Pentium Pro was also the first Intel microprocessor for some years not to use the venerable Socket 7 form factor, requiring the larger 242-pin Socket 8 interface and a new motherboard design.

The Pentium Pro differs from the Pentium in having an on-chip Level 2 cache of between 256KB and 1MB operating at the internal clock speed. The siting of the secondary cache on the chip, rather than on the motherboard, enables signals to get between the two on a 64-bit data path, rather than the 32-bit path of Pentium system buses. Their physical proximity also adds to the performance gain. The combination is so powerful that Intel claims 256KB of cache on the chip is equivalent to over 2MB of motherboard cache.

An even bigger factor in the Pentium Pro's performance improvement is down to the combination of technologies known as "dynamic execution". This includes branch prediction, data flow analysis and speculative execution. These combine to allow the processor to utilise otherwise wasted clock cycles, by making predictions about the program flow to execute instructions in advance.

The Pentium Pro was also the first processor in the x86 family to employ superpipelining, its pipeline comprising 14 stages, divided into three sections. The in-order front-end section, which handles the decoding and issuing of instructions, consists of eight stages. An out-of-order core, which executes the instructions, has three stages and the in-order retirement consists of a final three stages.

Pentium Pro CPU architecture

The other, more critical distinction of the Pentium Pro is its handling of instructions. It takes the Complex Instruction Set Computer (CISC) x86 instructions and converts them into internal Reduced Instruction Set Computer (RISC) micro-ops. The conversion is designed to help avoid some of the limitations inherent in the x86 instruction set, such as irregular instruction encoding and register-to-memory arithmetic operations. The micro-ops are then passed into an out-of-order execution engine that determines whether instructions are ready for execution; if not, they are shuffled around to prevent pipeline stalls.

There are drawbacks in using the RISC approach. The first is that converting instructions takes time, even if calculated in nano or micro seconds. As a result, the Pentium Pro inevitably takes a performance hit when processing instructions. A second drawback is that the out-of-order design can be particularly affected by 16-bit code, resulting in stalls. These tend to be caused by partial register updates that occur before full register reads and they can impose severe performance penalties of up to seven clock cycles.

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