Finding And Analyzing The Longest Combinational Paths In Rtl Designs Using The Blue Pearl Software S

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Shakeel Jeeawoody
Director of Marketing
February 2012

The demand for fast, mobile and integrated devices is relentlessly on the rise. However, these devices need to be delivered in ever shorter timeframes due to cost and time-to-market pressures. The development of these complex devices requires the use of new and innovative EDA tools for successful and timely tapeouts since design teams are increasingly facing tougher challenges to meet performance requirements.
Blue Pearl Software assists design teams to minimize the risks of not meeting performance goals. Blue Pearl has been long known for its automatic SDC constraints generation capability, which reduces the frustrating “ping-pong” game between the RTL design and backend teams within a given project. The manual method of writing SDC constraints is incomplete and it causes a perceived need for “experimentation”; Blue Pearl’s complete set of SDC timing exceptions clearly reduces the number of iterations for any product development team.
"Learn More How Blue Pearl Software can help FPGA designers"

With the latest release of its ...
... software suite, Blue Pearl went one step further in providing early assistance to designers to identify issues that would prevent them from meeting their performance goals. Instead of waiting for synthesis or place and route results, designers are able to use the longest path analysis feature in Blue Pearl’s software suite to identify timing critical paths directly from their RTL designs. Users can specify the maximum combinational levels allowed for the design or block, and the tool will find those paths that violate the user-specified combinational depth for each of the categories: flop-to-flop, port-to-flop, flop-to-port, and port-to-port. Several options available for this feature enable the designers to focus quickly on problem areas. During the path identification phase, designers can select which end-points they are concerned with, which clock they want to limit the analysis to and what maximum fanout is allowed. Additionally, during the debug phase the designers can specify how many of a particular violation they want to see, and utilize the various filtering criteria to zoom in to a specific path of interest.
The above figure shows the results of port-to-port violations on the left, and a path with 41 combinational levels on the right.
Initial feedback from our customers indicates that the longest path feature reduces their design cycle by weeks. Instead of multiple, long iterations in synthesis and/or place and route together with timing analysis tools, designers now use Blue Pearl’s software to identify the longest timing paths. The added benefit is that front-end designers, who understand the design better than the back-end team members, can make the required changes early in the design cycle when the design is still at the RTL stage.

To learn more about the Blue Pearl Software Suite, please visit our website at www.bluepearlsoftware.com. Additionally, Blue Pearl is offering