Ccie R&s 4.0 Blueprint Announced

By Author: pangsiyan
Total Articles: 130
Comment this article

The 4.0 version of the CCIE R&S Lab Blueprint is instilling a sense of reality into the world. Part of this came from the CCIE Program's self-analysis.

What basically we did, said CCIE R&S Program Manager Maurilio Gorito, was validate our Blueprint through job/task analysis. A couple of external CCIE and SMEs worldwide, and a couple of internal CCIEs were asked what they were doing at an ‘expert' level and we tried to validate our blueprint.
The good news, according to Gorito, was that the 3.0 blueprint was generally avalid list of topics. Topics, however, do not necessarily equal methods. One of the first things readers will notice in the 4.0 version of the blueprint is that there
really isn't much missing. Well Ok, Multicast DMVPN has finally been removed.
And Layer2 Tunneling has met a silent demise.
What else? Ummmm Nothing that really leapt out at me, and nothing that was highlighted in my conversations with CCIE team members.
Next, the interesting newsFormat changes! A full-fledged troubleshooting section will be added into the CCIE R&S Lab exam (other tracks will ...
... follow). This,much like the Core Technology Questions, will be a completely separate test
portion.
Just in case you were wondering, the Core Technology Questions are here to stay. So you now get a three-part exam. Just when you thought it was safe. How paranoid are you feeling now?
The funny thing is that you shouldn't feel paranoid at all. Candidates that study through the technologies should be able to handle either the Core Technology Questions or the Troubleshooting Section without much difficulty! So why
are people going to be paranoid anyway? Because it's something new. It's something nobody has talked about. And therefore we fear the unknown.
Everything in the CCIE lab is about thought process though. If you treat the new things like anything else, you'll find a process and will be successful at it! (Well,with practice anyway). I am quite excited about the addition of a troubleshooting section to the lab exam!
Granted, I don't have to go take the test again, but I have thought for the past six years that the troubleshooting was something sorely missing from the lab exam. In case you were wondering, the old two-day labs had a troubleshooting
section. Although a different focus than the upcoming troubleshooting, it was still a different process to think through!
According to Gorito, the total lab will still be an eight-hour exam. We are not adding hours to the day.
There is no minimum time to spend on a section [of the lab], he adds, but there will be maximum times.
Just like candidates are becoming used to in the current exam format, once you tell the system you are finished with one section (the Core Technology Questions in today's lab), you cannot return to it.
The grading mechanism will change with the new lab as well, although full details aren't going to be released as is common with any of the lab exams.
The candidate will need to pass in all three sections in order to pass the exam,Gorito stated.
He did offer a little insight to the Troubleshooting section though. Candidates may find a single Trouble Ticket comprised of just one problem. Or you may see one with more than one issue to figure out. He alluded to the idea that 2-3 issues may be seen within a Trouble Ticket, but nothing more.
So we've had the shock. Seen the good news (no matter how small) Seen the interesting news Like everything, there's always a bad news portion.Want the bad news?
Well, there are a significant number of things that are ADDED to the 4.0 blueprint! What? Added? Keeping the Core Technolgoy Questions Adding in Troubleshooting When are candidates going to have time to actually do any
real work, let alone adding new technologies in here?
Excellent question! The short answer is that not every lab exam will cover every single thing on the blueprint. That has always been one of the unspoken rules of the CCIE lab. Well, that and Anything is Fair Game! But with an increased
scope in topics, and a decreased amount of time available, that will definitely change both the depth and breadth of topics covered in any one single exam.
Many of those topics have HUGE implications on what could be involved. Just remember that many of these topics also exist on other CCIE tracks. While the R&S Track is indeed the largest (and therefore it must be the coolest track
(smirk)), it is not attempting to take over the world.
When asked about the impact on the WAN we have all become used to seeing on the CCIE labs, Gorito says We are not replacing Frame-Relay with MPLS. We are introducing MPLS.